CAS and LLSC was High Level buttembler for MVS & VM & VSE 1120

Reading was accomplished by splitting a bubble into two, and sending one down the read path while the other continues in the storage loop.

All of the storage in the bubble memory chips was organized as shift registers. If you want to read a particular set of bits, you have to wait for them to come around to the read position, just like shift registers or disk drives.

In order to keep access time reasonable, bubble chips are organized as many storage loops and a separate I-O path (which may or may not also be a loop). Logically the data is considered to consist of pages, where a page consists of one bit in each storage loop, such that all of the bits in a page can be simultaneously transferred to or from the I-O path.

The maximum access time is thus to a first approximation the product of the cycle time of the applied rotating magnetic field and the length of the storage loops.

Because of physical geometry constraints, the transfer points between the storage loops and the I-O path are usually spaced more than one position apart on the I-O path. In principle if they are spaced every fourth position, it should be possible to efficiently read or write to four consecutive pages. I'm not sure whether the commercially available bubble memory systems took advantage of this capability.

Certainly they were used for program store, but in the same way that a disk is used for program store.

IIRC, the PDP-11 Unibus was designed to support read cycles that don't restore the core contents, for use when they are about to be overwritten.