Cache Memory Chips
At first there was the CPU 1)Then they added index registers 2)Then they added general (& special purpose) registers The general purpose registers were THE fastest accessible memory. They were(are) separately visible with their own addressing scheme 3)Then they added block transfers from to main memory. The idea was that probably other data from the fetched block was more likely to be used next. So bring it closer to the CPU 4)Then they added extended memory Slower than the main memory but less expensive. It was used for buffers, and even ram (hyper) disk 5)Then they added cache, and started introducing cache Debt Management schemes. First cache, then L1 cache, then L2 cache. 6) In the other direction virtual memory was extended via i-o to slower storage hierarchies. 7) There was-is also such things as separate caches for partially decoded instructions. These stores are implemented using the same fastest technology as the CPU, active registers, at the CPU. 8) Also there are-were some architecture designs with very large register sets. The idea is to be able to switch between blocks of registers (fastest memory) fast for context switching.
One thing that could possibly be done to decrease time lost in shufling data between cache hierarchy levels, would be to make the levels directly and independantly addressible. It would need to be done at the machine instruction design level. i.e. the addressing would need to cost instruction bits just as addressing registers does now. The other extremely high cost would be the loss of flexibility in the sizing of a machine.
Military Time 2899
John D. Slayton 360s had a 32bit, binary timer ... located at location 80 (hex '50') in real storage. it was about 15hr period ... and most machines updated it...
Military Time 2900
Gene Cash note that the 360 just had the cpu timer (at location 80) ... and everything else was done in software. 370 introduced the...