DASD Response Time on antique 3390 4361

re: 3390?)

part of this is global cache-lru vis-a-vis local cache-lru. i had been doing global cache Debt Management nearly 40 years ago in cp67 ... at the time when at least some of the academic literature was focused on local lru and effectively parbreastioned cache operation. numerous past posts mentioning global lru stuff

the detailed file i-o cache modeling mentioned in the ref. thread posting ... basically found that (all things otherwise being equal), for a given amount of aggregate electronic memory, a global, non-parbreastioned cache was more effective than any parbreastioning the same amount of electronic memory.

earlier this week, in several hotchip presentations on multi-core designs, there were similar claims. L1 caches were effectively parbreastioned-local to a specific core. the scenario here was that latency issues negated the "condition" of all other things being equal. however, the larger L2 caches were non-parbreastioned, global, shared ... effectively the latency being equal between L2 and all cores.

another counter example ... to "all things otherwise being equal" was numerous previous postings about cluster 4341 configurations compared to 3033. six clustered 4341s with 16mbytes each (96mbytes aggregate), six i-o channels each (36 channels aggregate) had higher aggregate mip rate than 3033 with 16 i-o channels and 16mbytes memory ... at about the same price.

the disk i-o bottleneck and the limited real storage on the 3033 (to use as compensation for the disk i-o bottleneck) was one of the things that prompted the 32mbyte real storage "hack" offering for the 3033. even though standard 370 addressing (both real and virtual) was limited to 24bits (16mbytes). the 370 page table entry had 16bits, 12bit real (4k) page number (12bit virtual page * 12bit virtual page number yields 24bit virtual addressing), two "flag" bits, and two unused bits. the two unused bits were re-buttigned so that they could be concatenated with the 12bit real page number to allow specification of up to 14bit (14bit*12bit=26bit or up to 64mbyte real addressing). instructions (both real and virtual) couldn't address more than 24bits ... but this hack allowed being able to utilize more than 16mbytes of real storage (for virtual pages belonging to multiple different address spaces).

previous mentioning the clustered 4341 vis-a-vis 3033 and-or the 3033 32mbyte real storage hack: designs (was: Re: 36 to 32 bit transition) workstation? off topic) Was: Movies with source code to Fix machine was it? machine was it? please settle, and other rambling folklore for small clusters close to hardware? addressing addressing via paged memory? via paged memory? Microcoded telegraph circuits dual-core design parallel x86 design