IBM 610 workstation computer 3393

This is a difficult topic to teach. The serialisation that is implicit in the "von Neumann" model is so intertwined with the teaching of entry to intermediate logic that it becomes difficult to separate them.

The normal style inherent in

int i;

There has been a lot of work done to alliviate the worst implications of this. Micromachines often use architectures like VLIW and other forms of inherent parallellism; but they have to support the serial, imperative ISA.

Interestingly, the current architectures will do the "word at a time" exercise in a small, very fast cpu-internal core; and stream the write of the whole array as a single (or a few) operation(s) to memory.

So, hardware is already doing this; but software is becoming the huge limiting factor.

Also systems like SQL tend to go in this direction; where they operate on groups of data as an enbreasty.

It just shows how extremely bottoms-up the whole toolchain is, and the mindset has been influenced by it. And new languages keep making the same new errors.

We need to dispense with what I call the "imperative model", where you specify in minute detail the 'how'.

We need to build blocks that concentrate on the 'what's and then let the current arsenal of code generators etc. solve the 'how'. Give the compilers a lot more scope to work in. In the next step we can then utlize a score of slave processors to do the nitty gritty of the 'how'.

You don't have to go quite as far. But you need to get over the need to be imperative, and depend on declarative approaches.

Or, you let the compiler back end see to it that it is implemented in an effective fashion on the hardware of the day. But then you need to tell it enough of your intentions to do a good job of it.

Today we tell the compilers (and toolchain in general) extremely little about what we really want to do.

-- mrr