IBM 610 workstation computer 3404
Snooping is a completely different kettle. Heisenburg's Principle applies here. Even on machines built in simpler times, the snooper had to be very careful that the snooping didn't affect the measurements he was collecting. You could gather performance data, design a project, implement it, only to find that you only improved thruput when you're snooping. JMF had a DECUS session on this kind of stuff. But I don't remember when.
I'm not talking about memory. One of the things you guys seem to be confusing is what "external" and "internal" memroy to the CPU means. ISTM that you need to do a paradigm shift and begin to think of CPUs and their caches as a system rather than a CPU. I'm not saying this very well.
No, it isn't shared. It is a single source.
You're asking for lots of troubles if you're doing the equivalent to writing your shared high segment. This is memory Debt Management and should not be left entirely to hardware machinations. The hardware guys will always choose the wrong thing to do. They don't think in OS and user service delivery terms; they think in electrical engineering terms which they are paid to do.
IBM 610 workstation computer 3405
lots of cache implementations have significant (direct) cross-cache chatter about what cache lines they have (cache coherency protocols). multi-level L1, L2, L3 cache architectures...