IBM 610 workstation computer 3405

lots of cache implementations have significant (direct) cross-cache chatter about what cache lines they have (cache coherency protocols).

multi-level L1, L2, L3 cache architectures were discussed from at least the early 70s. some more recent convention was when L1 was on-chip ... and L2 was off-chip. then as chips starting getting larger number of circuits ... they were able to move L2 on-chip also.

801 from the 70s was strongly against cache coherency. I and D cache were separate and non-coherent ... and the early 801s had not provisions for cache-coherent smp-multiprocessing.

i've often claimed that this was in strong re-action to the performance penalty that the mainframes paid for very strong memory model and multiprocessor cache coherency. however, this is a reference to a mainframe with separate I and D cache ... where there was hardware cache-coherent between the two caches:

one of the issues in the 801 with separate non-coherent I and D cache has to do with "loaders" ... function that loads programs into memory preparing them for end. loaders may treat some amount of the program as data ... resulting in modified areas of the program being resident in the D (data) cache. in such schemes, the loader needs to have a (software) instruction to force modified D cache-lines to RAM ... before starting program end.

eventually somerset project (austin, motorola, apple, et al) basically undertook to redo 801-rios-power for lower-power, single chip, cache coherncy, misc. other stuff (i've somewhat characterized it as taking the multipleprocessor motorolo 88k stuff and some basic 801-power) ... to creat the power-pc. the executive that we had been reporting to when we were doing ha-cmp

moved over to head up somerset. misc. postings on 801, romp, rios, power, power-pc, etc

other approaches were snoopy cache protocol ... like sequent used in the 80s. also IEEE sci standard used a dictionary lookup cache protocol to get some more scallability (and numa ... non-uniform memory architecture) sci web pages:

for other topic drift, lots of posts on multiprocessing, compare&swap instruction, caches, etc

misc. past postings on numa, sci, etc

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