IBM 610 workstation computer 3414

there is two types of software support ... one is actually hardware cache coherency and the other is smp processing coherency ... but frequently refered to as serialization (aka coherency-consistency is maintained by enforcing specific serialization).

the 801-risc separate I(nstruction) & D(ata) caches from the 70s weren't hardware coherent. for the most part this didn't surface the software level although it precluding any of the self-modifying instruction operations that were found in 360-370. it did surface for program loaders which tended to treat sequences of instructions as data ... which might result in modified cache lines (containing) instruction appearing in the (store "into") data cache. loaders than had special instruction that forced changed cache lines from D-cache back to memory ... so that when I-cache went went to pickup the cache line from memory, it would have any changes done by the loader.

801-rios had no cache coherency (somerset was project to do an 801-like smp cache coherency and a single-chip implementation for the power-pc). however there was an early 4-way "smp" 801-rios using a chip that was called ".9" (or single-chip) rios ... but didn't have cache coherency. what was doine was an additional flag was added to the segment registers ... this flag controlled whether data operations used standard d-cache operations or completely bypbutted d-cache and alway used values directly from memory. software then had to sensitized to what stuff would be cache'able (and fast) and what stuff woulc be non-cache'able (slow, but consistent).

one of the things that was done for examplar was a mach (from cmu) kernel implementation where the smp processor complex could be configured (parbreastioned) as multiple clusters with a subset of the processors. between the clusters, message pbutting i-o paradigm could be simulated with memory-to-memory operations.

there was also software stuff about whether memory from (slower accessed) numa banks was used directly or if it was first copied to closest-fastest numa memory bank (for the specific processor).

this somewhat harks back to the 360 days (in the 60s) with 8mbyte-8mic LCS. you found these boxes installed on 360-50 (main memory, 2byte, 2mic) and 360-65s (main memory, 8byte, 750nsec). you found some configurations using the slower 8mbyte LCS memory bank as extension of standard storage ... and other congfigurations that used the 8mbytes more like fast disk ... that would copy data &-or programs between LCS and standard, faster memroy. you found some installations mixing the two modes of operations ... sometimes using LCS as straight-forward extension of standard memory and sometimes using it as fast electronic disk ... copying data-programs between LCS and regular memory.

for some topic drift, connection between ampex and oracle:

misc random other web refs curtesy of search engine

and for further relational drift, collected posts on original relational-sql implementation

ampex was one of the manufactures of LCS ... they had this building west of 101, south of sanfran. some past posts mentioning ampex:

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