IBM 610 workstation computer 3443
As long as we agree on the definitions, I'm not too interested in what it's called. ;-)
IBM 610 workstation computer 3447
Who is the I in this last sentence? I am stating that the I is the OS. It cannot...
The L2 caches are available to all CPU ports, that's exactly my point. I haven't seen this in Andrew's proposal, which is one of the reasons, IMO, that his idea won't work. Caches do; proof = existence.
IBM 610 workstation computer 3444
are memory cache board. main is a Sure. But we are viewing the system from differently shaded glbuttes :-). That's where we get into great communication problems...
Huh, you were just arguing that data will be inconsistent if all CPUs don't see the same image of memory. With an appropriate cache snooping protocol the memory image is consistent.
I-O can't be cached since events external to the system are changing the data. Any processor caching I-O locations will have stale data. I-O generally has to be done in-order, as well. Caches aren't appropriate for I-O, regardless of where the bottleneck is.
Nope. Only his tag in the cache that says that CPU owns the data exclusively. It's the caches' job to keep data ownership straight and there are several protocols for this.
It covers it quite well. That "existence" thing again. ;-)
AFAIK, that's what Andrew is proposing. I just stating what *is* and why I don't think his proposal will 1) work, and 2) be of any practical use if I'm wrong on 1). ;-) I *know* write-back caches work for SMP systems.
IBM 610 workstation computer 3445
snip In most (but not all) systems less than 10% of the memory contains writeable global data. The application software knows the name of these areas and gains access to them via the operating system...
Eight AMD Opterons get along quite well over their coherent Hypertransport fabric. PowerPCs do quite well, eight plus L3 on one module.
Every item in the caches, sure. There are several such "keys"; Valid, Dirty, perhaps Exclusive, Shared...
No, memory is slow. Caches aren't comparatively.
No, more like the guys in the striped shirts are making sure all the rules are obeyed.
Well, threads have to make sure they don't step on each other, but this is true even for UP systems, no?
Only up to a hundred thousand processors, or so. ;-) Seriously, PowerPC (Power4-5 etc.) does 8-way SMP as a basic building block. Intel x86 is at least 4-way and AMD Opterons up to 8-way without bridges, though NUMA not SMP. Opteron's NUMA is coherent, though.