Lit. Buffer overruns 1725

charlie invented compare-and-swap at the science center

working on fire-grain locking for cp67 (he observed that majority of the requirements was for updating storage location ... which was somewhat different semantics that the TEST&SET instruction available on the 360-67). one of the tasks buttociated with getting compare-and-swap into the 370 architecture was coming up with a mnemonic that matched charlie's initials (CAS). Before availability, it was decided to do both compare-and-swap and compare-double-and-swap ... resulting in the actual buttembler mnemonics being CS and CDS.

the other problem was that the owners of the architecture in POK said that it wasn't going to be possible to justify a new 370 instruction for purely SMP ... that a use-justification was needed that was only applicable to purely uniprocessor machine. That spawned the use of atomic instruction in multi-thread applications (like databases) that were enabled for interrupts ... and that after an interrupt control might be resumed with a different application thread. This gave rise to the compare-and-swap instruction programming notes in the 370 principle-of-operations ... that quickly found their way into the appendix.

360-370 had some number of RMW instructions that weren't defined as atomic; and, or, exclusive-or, etc. (they were non-interruptable, but weren't defined to be SMP-safe-atomic).

I had worked with charlie and reworked my dispatching, scheduling, resource management, paging, etc to be multiprocessor-sensitive (a lot of which I had originally done as an undergraduate). In the morph from cp67 to vm370, a lot of that was dropped.

Later, I got to put a lot of it back when they let me do the resource manager:

At about the same time, I was also doing a SMP project that used extensive microcode support for much of the infrastructure

however, vamps was canceled before it shipped. much of the design was adapted to a software only SMP implementation for ship as product.

a problem was that it was heavily dependent on kernel organization that was already part of the shipped resource manager.

the industry was going through a shift from free (& shipping source code) software to priced (and eventually OCO ... object-code-only). some application code had started being charged in the unbundling of 6-23-68 plus 1 but kernel code was still free ... and we did full source code shipment as well as source code maintenance.

somewhat because of clone processors and other factors, there was a decision to start charging for kernel code. the resource manager was selected to be the guinee pig ... and i got to spend six months on and off with the business people working out the business practices for charged for kernel code. at that point the decision was that kernel code could be charged for that wasn't directly involved with hardware support (like resource management).

so the problem with the smp support was that it was directly involved with hardware support and therefor free. however, it was heavily dependent on code in the resource manager which was already shipping as priced software. the decision was finally made to move something like 80 percent of the code in the resource manager to the free kernel base (but continue to charge the same price for the reduced code resource manager).

lots of other SMP posts:

370 principle of operations (warning 31mbytes)

much of the compare-and-swap programming notes were in the appendix (pg. 310-314 in the above).

more recently the PLO (perform locked operation) instruction has been introduced.

compare and swap

compare double and swap

more recent perform locked operation

test and set (still around from 360 days)

appendix A.6 Multiprogramming (multi-thread) and Multiprocessing Examples

appendix A.6.1 Example of a program failure using OR immediate (non-atomic RMW)

the rest are bits and pieces from the original 370 POP programming notes (used to justify getting compare-and-swap in the 370 hardware)

appendix A.6.2 Conditional Swapping Instructions (CS, CDS)

appendix A.6.3 Bypbutting Post and Wait

appendix A.6.4 Lock-Unlock

appendix A.6.5 Free-Pool Manipulation

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