Misuse of word "microcode" 100

the 370 115-125 were another interesting microcode machines.

the basic machine had a shared memory bus with ports for up to nine processors. a typical 370 115 configuration might have 4-6 identical processors installed; one with microprogramming to implementing 370 instruction set and the rest with microprogramming implementing various device controller functions (disk, tape, communications, etc). the native processor engine was about 800kips which with the 370 microprogram load delivered about 80kips 370 (approx. 10:1 ratio).

125 was identical to the 115 except a faster native processing engine was used for the 370 function. the native 125 370 processor engine was about 1mips yielding approx. 100kips 370. otherwise the rest of the hardware configuration was the same as 115 (possibly 2-8 800kip processor engines loaded with various kinds of device controller microcode).

in the 70s, i worked on VAMPS design;

special 125 smp implementation where up to five of the shared memory ports would be occupied by 370 processor engines.

i migrated much of the dispatching logic into the microcode of the processor engine ... and the kernel software would queue and dequeue tasks ... but the machine microcode actually handling dispatching of tasks on specific processors (somewhat analogous to i432 migrating multiprocessing dispatching into the silicon of the machine).

i also did a higher level queue-dequeue for disk i-o operations ... somewhat akin to what was found in later 370-xa that appeared with the 3081 ... discussed in previous post:

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