REAL memory column in SDSF 4604

processing latency ... this was if you would to do multiple consecutive full track transfers ... with head-switch to different tracks (on the same cycliner; aka arm position) w-o loosing unnecessary revolutions ... aka being to do multiple full track transfers in the same number of disk rotations.

as already discussed (in some detail) ... 3880 disk controller processed control commands much slower than the previous 3830 disk controller

which met that it was taking longer elapsed time between commands ... while the disks continued to rotate.

there had been earlier studied in detail regarding elapsed time to do a head switch on 3330s ... in order to read-write "consecutive" blocks on different tracks (on the same cylinder) w-o unproductive disk rotation. intra-track head switch (3330) official specs called for a 110 dummy spacer record (between 4k page blocks) that allowed time for processing the head switch command ... while the disk continued to rotate. the rotation of the dummy spacer block overlapped with the processing of the head switch command ... allowing the head switch command processing to complete before the next 4k page block had rotated past the r-w head.

the problem was that 3330 track only had enuf room for three 4k page blocks with 101-byte dummary spacer records (i.e. by the time the head switch commnad had finished processing, the start of the next 4k record had already rotated past the r-w head).

it turns that both channels and disk controllers introduced processing delay-latency. so the i put together a test program that would format a 3330 track with different sized dummy spacer block and then test whether a head switch was performed fast enuf before the target record had rotated past the r-w head.

i tested the program with 3830 controllers on 4341, 158, 168, 3031, 3033, and 3081. it turns out that a 3830 in combination with 4341 and 370-168, the head switch command processed within the 101 byte rotation latency.

combination of 3830 and 158 didn't process the head switch command within the 101 byte rotation (resulting in a missed revolution). the 158 had integrated channel microcode sharing the 158 processor engine with the 370 microcode. all the 303x processors had a external "channel director" box. the 303x channel director boxes were a dedicated 158 processing engine with only the integrated channel microcode (w-o the 370 microcode) ... and none of the 303x processors could handle the head switch processing within the 101 byte dummy block rotation latency. the 3081 channels appeared to have similar processing latency as 158 and 303x channel director (not able to perform head switch operation within 101 dummy block rotation).

i also got a number of customer installations to run the test with a wide variety of processors and both 3830 controllers and oem clone disk controllers.

misc. past posts discussing the 3330 101-110 dummy block for head switch latency: