Reviving... the Bline
On my web page, at
Some time ago, I had learned that the Philco 2000 computers used their index registers as pointer registers, rather than as misnamed base registers, because the selector bit changed the...
I describe a minimalist 32-bit instruction format to allow a bank of 64 ALUs (64 integer ones and 64 floating-point ones, actually) to also serve as 64 independent computers running in MIMD mode, in addition to accelerating SIMD vector instructions, or permitting 65-way superscalar computing in conjunction with the main ALU.
It is drastically simplified over a previous iteration.
and the precursor to PLO is compare-and-swap ... done by C.A.S. at the science center the first thing had to come up with was a mnemonic...
So simplified that it doesn't even allow specifying index registers.
Well, after I announced that on my web page at
I described, with color coding and graphical symbols a wide variety of floating-point formats, I received an E-mail commending the 39-bit Elliott 803 computer to my attention.
While I had already described only a small number of the possible floating-point formats I could have dug up on that page, another architectural feature of that computer caught my attention. I was already using the postfix supplementary bits in my architecture for many strange purposes, why not add one more?
But that sort of thing made a poor fit to a variable-instruction-length architecture that already had index registers. However, greatly modified (one can't change the opcode any more, for example) I did find a use for it with my plain two-address format for those 64 MIMD processors, so as to allow a sort of indexing.
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