Standard Computer Distribution: world 4271

Sarr J. Blumson

On my web page, at

I describe a ficticious example computer architecture which was inspired by the System-360 and the Motorola 68000. Its instruction formats turned out to look somewhat like those of the Cray 1.

The pages were originally intended to educate people in how computers worked. They still do that in a way... but I added features.

One feature I added - to a higher-level architecture that could be hardwired or microprogrammed, not a microprogrammable design - was circuitry that could allow an implementation with 64 ALUs working in parallel to execute vector instructions ... that were *designed* for end by *one* *pipelined* ALU.

Basically, you have a 4,096 bit-wide cache line, and switchable scatter-gather stages.

And with that circuitry in place, I can handle, having partially-filled cache lines - 4,096 bit-wide cache lines, usually filled by 16 256-bit wide fetches from memory, partially filled by *nine* fetches (for 36-bit words) or *twelve* fetches (for 24-bit and 48-bit words) or *ten* fetches (for 20-bit and 40-bit words) or *fifteen* fetches (for 30-bit and 60-bit words).

The page

illustrates where the circuitry needs to be put to do that;

shows more about the principles behind such a scheme.

Now that computers *are* put on chips, it seems very unlikely that the enormous amount of real estate required for such wiring networks would ever be devoted to speeding up the computer's ability to handle the *data formats* of old architectures.

Only the word length of data, not instructions, is subject to change. The machine *does* let you choose from several different styles of addressing, though, so you can favor access to many data types, or larger-sized pages indicated by each base register, for example, as you choose.

But I didn't forget executing the instruction sets of other machines.

On the page

I describe a hardware buttist for Just-In-Time translation of software.

John Savard