Tru64 and the DECSYSTEM 20 1078

the issue is what you call power and what you call power-pc. original power was rios ... absolutely no cache coherency and no capability for consistent shared memory multiprocessing (live oak was 4-way with rios.9 chips where virtual memory segments were defined as cacheable or not cacheable ... aka smp coordination was achieved by forcing non-cached memory).

somerset was started with motorola and apple ... to do several things ... one was supporting cache consistency and smp. one might claim that part of power-pc by somerset sort of had 88k bus and cache consistency applied to an 801 infrastructure. these were the 601, 602, 602, 603, 620, 630, etc. original as-400 port to risc used some flavor of 6xx chip. 64-bit 620 design meetings had rochester demanding 65-bit (as opposed to 64-bit) ... where they needed the 65th bit for special tagging.

when we started ha-cmp

we reported to an executive that then went over to start somerset (he had originally came from motorola). he got somerset rolling and then left to become president of mips ... and turn out the 10k.

trusty search engine use turns up as-400 and apple using same power-pc chip

from above:

The chip used in a PowerMac and the IBM eServer pSeries (RS-6000). A very close variant of PowerPc is also used in the IBM eServer iSeries (AS-400).

... snip ...

from above:

The IBM AS-400 will be reborn by the mid-1990s with a new 64-bit reduced instruction set computing (Risc) microprocessor that will also computers, according to a report issued byADM Consulting, Inc.,

... snip ...

from above:

If your move is a CISC-RISC, see the appropriate 'AS-400 Road Map for Changing to Power PC Technology' manual for more information.

... snip ..

more trusty search engine use turns up random refs to as-400 power-pc

--