Using the Cache to Change the Width of Memory 372

Having a cache that has a 4,096-bit wide data path to 64 ALUs in parallel requires some way to allow these ALUs to operate on consecutive bytes, halfwords, or words in addition to doublewords.

I had worked out a way to do this with a limited amount of circuitry; by performing first global scatter operations over the 4,096 bit width of the bus, and then local gather operations over the 64 bit width of the data path into each ALU, I just needed two sets of interconnects.

Even if I decide I don't want to perform repeated operations with the same circuits, requiring a buffer (although such an operation should be rapid enough so as not to exceed the size of a pipeline stage), the principle can still be used as a guiding principle to simplify the wiring of the unit.

But what happens when I use a 48-bit word, or a 36-bit word? Or, for that matter, a 40-bit word, or a 60-bit word, as I have also defined as possibilities? Does the special circuitry go before, or after, the scatter-gather unit, or will I need to have a scatter-gather unit for each width?

I hadn't worried to much about this detail, but I have now realized the solution.

Prior to the scatter-gather unit, globally, across the full 4,096-bit width of the bus, unpack 6 bit characters, putting them into eight-bit bytes, or unpack 9, 10, 12, or 15 bit characters into 16-bit halfwords.

After scatter-gather, which puts the right number of bytes *and* halfwords in each 64-bit doubleword for the datatype one wants, do a local pack operation.

As with 128-bit operands, 72, 80, 96, or 120 bit operands will require two cycles to be placed in all sixty-four arithmetic-logic units.

I suspect all this is well-known in the art, even if I can't recall any references I might have seen ages ago.

John Savard