Using the Cache to Change the Width of Memory
On my web site, I had proposed a computer design which started out as a simple big-endian machine, say like a 68000 or a 360, but which added a lot of features, with which I illustrated various architectural concepts.
One thing I added was this:
Let's say the bus to memory is 64 bits, for example.
If I make 16 accesses to memory to fill one cache line, I can make the cache work really fast if I have an internal bus to the cache that is 16 x 64 bits wide.
Suppose I made only 9 accesses to memory, and called it a day for filling a particular cache line. Then, I could divide up this partially-full cache line into 16 words, each 36 bits wide. So even with conventional 64-bit wide RAMs, a little circuitry inside the chip lets me emulate a 7090 nicely.
Of course, interconnects take up chip space, so this is a costly and little-used feature.
*Question #1* - did anyone, perhaps back in the days when caches were made from fast cores, patent this idea?
Given a recent series of postings in comp.arch.arithmetic where someone advocated Burroughs-style architectures, it occured to me that this kind of architecture is well-suited to this kind of thing. Make a 10th access - add 4 bits of tag information to each 36-bit word. Or make a 13th access - add 4 bits of tag information to each 48-bit word. And so on.
Or one could do the same thing to add a field delimiter bit to 8-bit bytes or 6-bit characters.
Up-to-the minute technology... emulating the 1401.
This new addition to my design is not yet on the web, and I may not flesh out its implications fully.
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