VMS coming back to life 1295

wrote, in part:

While I do think that OpenVMS for the Itanium may not lead to a stampede of people adopting it, I am, despite the apparent evidence to the contrary, more optimistic about the future of the Itanium.

The Itanium, or IA-64, architecture is proprietary to Intel, and is claimed to provide certain efficiencies of program end not available from within either the IA-32 architecture or the EM64T feature. This doesn't seem to have been refuted soundly by any benchmarks I know of.

Current limitations of chip fabrication may still have made some directions of obtaining additional performance more attractive than others. If, however, at some time in the future, Intel were to include the Itanium instruction set architecture, in a modified form that includes all features available within the current x86 architecture (i.e., such things as SSE2), as standard within its latest generation of x86 chips, and if it were found in practise that programs taking advantage of this feature ran faster... then, that architecture would become standard, in much the same way as the 80386 superseded the 80286, and Intel would be in the position of being able to license the Itanium architecture to other chipmakers on its own terms (subject to the constraints of anbreastrust law, of course). Unless it is included in existing cross-licensing deals, despite no one else using it.

Given its deep pipelines, what the Pentium IV *really* needs is explicit vector instructions that use the pipelines, such as are found on Cray supercomputers. (Even better, of course: deeply pipeline the MMX-SSE arithmetic unit too, and have instructions that act on vectors which are in multiples of the length of the short vectors it handles.) Given the von Neumann bottleneck, even though in respect of their caches modern chips have a Harvard architecture, the slow path to main memory is such that efforts to shrink the number of bytes needed for the instructions in a program are of merit. This, however, is one of the areas of weakness in the Itanium's architecture, apparently.

I'm sure Intel will come up with something; they can look at their XScale processor, with the StrongARM architecture, for one example of how to shrink the instruction stream.

John Savard