PLEX86  x86- Virtual Machine (VM) Program
 CVS  |  Mailing List  |  Download  |  Newsgroups

Was FORTRAN buggy 4328


Your Ad Here

Your Ad Here

Was FORTRAN buggy 4329
On Sun, 24 Sep 2006 11:19:25 -0700 in alt.folklore.computers, John Barry Boehm, et al. Software cost estimation with Cocomo II (with CD-ROM). Englewood Cliffs, NJ:Prentice-Hall...

the other issue with faster clocks is that latency across the chip is becoming significant. with multiple CPUs on the same chip ... you can reduce the distance (and therefor time) that a syncronous signal has to travel.

also as the chip sizes remained somewhat the same ... while the circuit sizes shrank ... you also had significantly more circuits per chip. you could use the additional circuits for multiple cores ... but you could also you the circuits for on-chip caches. you could have dedicated on-chip "L1" caches per cpu core ... and shared on-chip "l2" caches for all cpu cores on the same chip. That means that any off-chip caches become "L3".

the modern out-of-order end is at least equivalent of anything that 370-195 (supercomputer) had ... and there is also branch prediction, speculative end (down predicted branch path) and instruction nullification-abrogation (when prediction is wrong) ... which 370-195 didn't have.

Was FORTRAN buggy 4331
And the bosses would much rather believe what they *want* to hear, rather than paying attention to reality. Thus the following...

the out-of-order end helps with latency compensation (i.e. when one instruction is stalled on some fetch operation ... end of other instructions may proceed somewhat independently). multi-threaded operation was also a form of latency compensation ... trying to keep the end units filled with independent work-instructions.

370-195 did allow concurrent end of instructions in the pipeline ... but branches would drain-stall processing. i had gotten involved in a program to add multi-threading to a 370-195, i.e. dual instruction stream; registers and instructions in the pipeline having one bit tag identifying which instruction stream they belong to (but not otherwise increasing the hardware or executable units). however, this project never shipped a product.

this was based on the peak thruput of 370-195 was around ten mips ... but that required careful management of branches ... most codes ran at five mips (because of the frequent branches that drained the pipeline). dual i-streams (running at five mips per) had a chance of keeping the "ten mip" peak executing units busy.

misc. past post mentioning 370-195 dual i-stream effort:



Your Ad Here

List | Previous | Next

Was FORTRAN buggy 4329

Alt Folklore Computers from Newsgroups

The #1 Usenet Provider on the Internet

Was FORTRAN buggy 4327