What ever happened to Tandem and NonStop OS 2022

370 virtual memory architecture was originally defined in such a way that TLB entries could be either STO-buttociative (aka address space) or PTO-buttociative (aka segment) ... but only STO-buttociative machines were actually built (aka many 370 operating systems would use common page table for segments shared across multiple virtual address spaces ... but furthermore, the 370 architecture was even defined such that such entries could also result in the same TLB entries).

370-168 TLB had 128 entries and was sto-buttociative (i.e. virtual address space). Each TLB entry had a 3-bit tag ... which corresponded to a 7-entry stack of saved segment table origin pointer (aka STO). If you changed STO register value ... it would look in the STO stack for match ... if not found, it would select a STO stack entry for replacement ... and purge all TLB entries that were buttociated with that entry (matching 3bit identifier).

peachtree ... which was used for series-1 ... had four level set of registers ... so it didn't need to save registeres between levels.

801 starting in the mid-70s

which was somewhat in re-action to the horrible complexity of future system project (which was canceled w-o ever being announced)

... in any case 801 ... had inverted tables and sizteen segment registers ... basically ... at least on romp ... you loaded a 12bit segment identifier ... and the TLB was segment identifier buttociative. this is somewhat where the 40-bit addressing write-up came from ... take the top 4 bits of the 32bit virutal address and select a segment register ... take the 12bit segment-id from the segment register and combine it with the remaining 28bits from the virtual address ... to get a 40bit "address". this sort of got contorted when trying to map unix (aka aixv2) on top of romp for pc-rt (instead of the cp.r virtual memory paradigm). some of this could still be lingering around for rios ... where the segment-id value was expanded to 24bits and some of the original rs6000-power documentation talks about 52bit addressing (as expansion of the 40bit address described for romp).

so for unix ... the 801 segment register values needed to be manipulated to simulate the more familiar virtual address space page tables (instead of a generalized virtual memory pieces appearing and disappearing with fairly high frequency). however, in this case, since the virtual address space was simulated with the segment-ids in the 16 segment registers ... they all have to be saved-restored in a context switch.

When I was doing the original fastpath work in the cp67 interrupt handlers ... there were cases where i could play games with what registers i needed to save and restore ... because, in some cases the interrupt might be handled directly w-o a real context switch ... and I would try and be very sparingly of what registers were used during the interrupt processing (aka analogous to some optimization of register save-restore that might be done in a subroutine call).

--