What ever happened to Tandem and NonStop OS 2023

Peter Flbutt

I'm agreeing violently.

I do, frequently.

In general silicon designers are not keen on big register files because as they get bigger they get slower, so you are looking at multiple register sets. The gotcha there is wire-delay, you need more plumbing & wires to make that go - so you take a hit on power consumption and clock-rate again.

Superscalar processors already use multiple physical register sets - see register renaming.

TLBs are a different problem, and one that has been tackled to some degree by "tagging" the TLB entries. These tags group entries together into protection domains so you can have several different protection domains resident at the same time. The prob then is the size of the TLB, it's gotta be big, if it's big it's slow, and of course it will get hit a lot, although less than a register file.

Shadow registers are kinda neat in principle, but they don't make much sense anymore in this era of register renaming. The trade- offs have changed a lot since 1970.

I know one guy who has a near "zero cycle" context switch on an FPGA core... However it's a bit of a con, the core is multi- threaded, but it also supports fine-grained memory management too, just the ticket for slicing up an OS into lots of itty bits. :)

Cheers, Rupert