Where should the type information be 121
There WAS some (relatively minor) interplay, as the stack architecture determined which instructions were likely to occur one after the other, which in turn affected how the systems that overlapped operation needed to be designed to minimize contention.
Yes, you are right that architectures can be mixed, but at the end of the day it must all play together. My point was that there was a gestalt to Burroughs' memory Debt Management and protection that was being lost in the discussions here, as people discussed how integers should (or should not) be marked as such, when they were a part of this grand plan.
Where should the type information be 123
snip Perhaps. I am not familiar with the details of the Burroughs implementation. If one had say a three dimensional array of 100...
GREAT caution would be needed here not to sacrifice software reliability in so doing something like this.
Of course, these days this would just be a cache hit.
Speeds are still comparable when you compare present CPU speeds to present cache speeds. Indeed, present caches are typically larger than RAMs were back then, so that present RAM is now really a form of secondary storage.
Where should the type information be 122
Steve Richfie1d I'm told it's been done - specifically, as I understand it, the AS-400 got it right. The key is to not store-distribute...
But not faster than an L1 cache hit.
YES, you have stated the issue. There are a number of reasonable possibilities given that the checking can be done AFTER the operation in the case of loads, and after the operation for stores if you mark the cache location as unchecked until it has pbutted checking. For even more speed, you can have enough array-descriptor registers to hold enough array descriptors for most loops, and run all array accesses through this mechanism.
I am NOT strongly opinionated as to which approach is best, but I DO believe that SOME efficient and required mechanism is needed to escape the present situation of flakey computers.
Does anyone else out there have ideas regarding how to make memory accessing safer? If we hand SOMETHING up for everyone to see, then there will be no more excuse for building unreliable CPUs.