Where should the type information be 123
Where should the type information be 125
And FWIW the original Tandem (later Compaq and HP) NonStop CPU, actually built (in mildly modified form) until IIRC 1992 and...
Perhaps. I am not familiar with the details of the Burroughs implementation. If one had say a three dimensional array of 100 X 100 X 100 elements, how many words of memory are needed for the descriptor? If one wants to protect each subscript instead of just the final address, then I presume you need three descriptors. And for all but the last one, the "description" is not of a contiguous range of adresses, but of a sparse set. Checking the correctness of those addresses requires more calculations than just a "range check". It seems that it would require some time to do. If, however, you have things set up sort of like C multi dimensional arrays, with pointers to consecutive locations of pointers for each dimension, then it will not fit in L1 cache and you will probably take at least one L1 cache miss for each access. How is that done in the existing implementation? How would it be done in your proposed implementation?
Where should the type information be 124
Since the postulated array occupies a contiguous region of memory, why would the descriptor need anything more than a base and...
Depends upon the implementation, as others have said here. But note also that if one is accessing the array sequentially, the multiply gets replaced by an add, and the cache hit is certainly slower than an add.
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