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Where should the type information be 124


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Since the postulated array occupies a contiguous region of memory, why would the descriptor need anything more than a base and a limit?

While my large systems days were limited, and were 20 years ago, my recollection is that the descriptor on the stack is simply a base-limit. IIRC there were tag bits buttociated with each memory word that indicated what the word held (a scaler, a descriptor, etc).

In the Large Systems architecture the subscripts will be read from tagged memory words (tagged as scalers) and be pushed onto the stack prior to being operated on. I don't believe that any descriptor is required for a scaler value.

Pseudo code:

PUSH K PUSH 10000 MULTIPLY PUSH I PUSH 100 MULTIPLY PUSH J ADD ADD PUSH ARRAYTOS

K: SCALER 0 I: SCALER 0 J: SCALER 0

The only instruction that requires a descriptor access is the last one. Range checking each individual subscript would require the compiler to generate the appropriate code.

Where should the type information be 125
And FWIW the original Tandem (later Compaq and HP) NonStop CPU, actually built (in mildly modified form...

Since the descriptor is already on the stack, and probably in the most recent activation frame, it is likely that descriptor access will hit any implementation-defined cache of the Top Of Stack words and be quite efficient.

This is all (mis)remembered from a clbutt I took in 1984 describing the A-Series (Large Systems at the time) architecture and may be incorrect in small ways.

scott



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Where should the type information be 123