Why no double wide compare and swap on Sparc 4386
the traditional locking on 360 multiprocessors had been test-and-set. charlie was doing a lot of multiprocessor fine-grain locking work for cp-67...
charlie had invented compare&swap as part of his work on fine-grain locking (leading to some number of lock free operations) for cp67 (360-67) mutliprocessor support at the science center
the trick then was to come up with a mnemonic that matched Charlie' initials, CAS.
the attempt was then made to get the instruction into the up and coming 370 architecture. working with ron smith in the pok 370 architecture group (they owned the 370 architecture "red book"), the response was that 370 didn't need another multiprocessor specific instruction, that the test and set from 360 was sufficient.
to get compare and swap into the 370 architecture we had to come up with useage for compare&swap that wasn't multiprocessor specific. thus was born some number of examples that were applicable to multi-threaded applications that might be running enabled for interrupts ... independent of whether the machine was single processor or multiprocessor.
originally in the 370 principles of operation, the examples were part of the programming notes that were part of the compare&swap instruction. in subsequent version of the principle of operations the examples were moved to a section in the appendix.
also as part of this activity, compare&swap double instruction was added in addition to compar&swap. that resulted in two instructions for 370, compare&swap along with compare&swap double ... so the instruction mnemonics become CS and CDS (instead of CAS ... defeating the original objective of coming up with instruction name compare&swap).
total topic drift ... science center was like that ... GML
from long ago and far away. To: wheeler On our previous subject . . . yes, I think you should contact Dr. Bill Worley. He has 801, new interactive software and some low end processors...
precusor to SGML, HTML, XML, etc ... also invented at the science center, actually are the first initials of the last name of the three inventors (and you probably thot it stood for generalized markup language).
misc. past posts on multiprocessor support and-or compare&swap instruction
esa-390 principles of operation appendix for multiprogramming (i.e. mulbreasthread) and multiprocessing
cs & cds appendix:
bypbutting post and wait
free pool manipulation
Alan Altmark writes: so one of the motivation for original dual-address space ... was that lots of mvt services (like hasp-jes) ran...
and more recent z-architecture (64-bit) principles of operation multiprogramming and multiprocessing examples appendix
note that the above also includes discussion of the newer PLO ...perform lock operation instruction
Why no double wide compare and swap on Sparc 4387
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