using 3390 mod9s 3192

ref:

part of the caching-electronic store discussions that on in the 70s had to do with global LRU and global caches vis-a-vis local LRU and parbreastioning.

as an undergraduate in the 60s, i had also done the global LRU stuff for cp67

about the same time, there was some work published in the literature about working sets and local LRU strategies.

in the early 70s, there was an effort by the grenoble science center to implement local LRU strategy for cp67 as per the academic literature. The cambridge science center

was running cp67 on 360-67 with 768k of real memory (104 pageable pages after fixed storage requirements) and my global LRU implementation. grenoble had a 360-67 with 1mbyte of real memory (155 pageable pages after fixed storage requirements). Cambridge with global LRU and 104 pageable pages basically supported about twice as many users (75-80) at the same performance and response as Grenoble support with local LRU and 155 pageable pages with 30-35 users.

in the late 70s about the time the disk activity project was gathering extensive filesystem-disk record access traces, which was then being used for various analysis ... including a cache simulator looking at various kinds of device, controller, channel, subsystem, and system caching strategies. except for some specific scenarios (device-level full-track buffer as compensation for rotational synchronization and things like RPS-miss) ... the modeling found that for any given, fixed amount of electronic storage (and all other things being equal), a single "system level" cache implementation always out-performed any cache parbreastioning strategy (i.e. some part of the electronic storage parbreastioned into device, controller, channel, etc caches).

About the same time (late 70s) there was a big fuss being made over a stanford phd effort that was basically covering the stuff that I had done as an undergraduate in the 60s. This stanford phd thesis was doing global LRU ... and some of the people that had been indoctrinated by the local LRU papers in the academic literature were objecting to the Phd being awarded (since global LRU conflicted with their LRU beliefs).

I was somewhat able to contribute to resolving the disagreement since Grenoble had published ACM article on their local LRU effort (in the early 70s) ... and I had hardcopy of some of their supporting performance data ... as well as similar data from Cambridge system doing local LRU (for apples to apples comparison of the two strategies running same system, same hardware, and similar workload).

in any case there is direct correspondence between the parbreastioning that occurs in local LRU cache strategies and the physical parbreastioning that occurs in device and-or controller level caches.

a couple posts that referencing the lru-clock thesis and related controversy replacement Login Names

misc. other posts mentiong the lru-clock countroversy Win95 without DOS...)) math skills to do data processing ? Grenoble France System-360 on 7 Apr 2004 for small clusters addressing before the ANSI C standard above the line boundaries