Open Source BIOS 3265

wrote on Thu, 02 Mar 2006 01:40:47 GMT

I'm not all that up on it but I do have an old memory book (somewhere) which mentions the RAS and CAS signals. It's actually fairly interesting, and the tech probably isn't all that different nowadays, although the signals are faster, the output bus wider, and the actual bits are physically smaller. Basically, CAS can refresh a "column" at a time; the address is multiplexed.

I'd have to look up the details but if memory serves the PC dedicates DMA channel 0 just for memory refresh. I don't think the software, BIOS, or anything has to do horribly special things here but it does tie up a channel. The 8088 only had 4 of them to begin with. (Remember IRQ 5, DMA 1 with the old SoundBlasters? :-) I do...)

I would also think any refresh would have to deal with contention issues, unless the system were designed so that part of an instruction cycle was dedicated solely to refreshing a column of memory.

The actual time per required refresh is probably heavily fab-process-dependent; IIRC 2 milliseconds (back in the 1980's) was the maximum a RAM bit could go and still guarantee that the bit won't dissipate its charge away. For a 1 GB stick that's 64 bits wide (11 bit multiplexed address buss) that translates to a refresh frequency of at least 1.024 MHz -- buttuming they're still using RAS and CAS, admittedly; I have no idea what the memory signals look like now.

Not all that taxing, actually -- but it does have to be done.

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